If you make a polygon on a plane layer, you will produce a region with no copper, not a region with copper. I don't know what the red trace in the RH box above is supposed to be doing - it's not on the same layer as the SMT parts and the via is obviously already connected to the through-hole pad through the plane. Plane layers are negative layers where copper is present on the entire surface, except where features are defined. Fewer vias is better for manufacturing but might be worse electrically and it might be better- only you know your circuit design. Polygons are positive features on positive (signal) layers, that fill large (or small) areas. Then other sources say create polygon pours after the connection is done.Īltium distinguishes polygon pours from plane layers. It might not be the one you expect, but by the time you connect all the pads to the planes, they should all be gone. As you connect each pad to the planes, you should see one netline disappear. Once signals are routed, turn the power and ground net ratsnest back on. Then they don't clutter things up while you're routing the signals. Generally I hide the ratsnest lines for power and ground pins during the initial part of the design. For example, a bypass capacitor next and the power pin for an IC placed near each other probably can share one via.īecause sometimes when I create via to each component then route their connection on the ground plane, the net line doesn't disappear all the time. But you might find cases where it's not needed. Each component probably has its own current draw so you want to have enough vias to accomodate that. Through-hole pads don't need another via - they already extend through the board to all layers.įor SMT, one via per pad is a starting point. Some said create vias to the ground planes.